By Ruy Luiz Milidiú, Artur Alves Pessoa, Eduardo Sany Laber (auth.), Michael T. Goodrich, Catherine C. McGeoch (eds.)
Symmetric multiprocessors (SMPs) dominate the high-end server industry and are at the moment the first candidate for developing huge scale multiprocessor platforms. but, the layout of e cient parallel algorithms for this platform c- rently poses a number of demanding situations. it's because the quick development in microprocessor velocity has left major reminiscence entry because the fundamental predicament to SMP functionality. seeing that reminiscence is the bottleneck, easily expanding the n- ber of processors won't inevitably yield larger functionality. certainly, reminiscence bus barriers usually restrict the scale of SMPs to sixteen processors. This has not less than twoimplicationsfor the algorithmdesigner. First, considering the fact that there are rather few processors availableon an SMP, any parallel set of rules needs to be aggressive with its sequential counterpart with as low as one processor to be able to be r- evant. moment, for the parallel set of rules to scale with the variety of processors, it needs to be designed with cautious recognition to minimizing the quantity and sort of major reminiscence accesses. during this paper, we current a computational version for designing e cient al- rithms for symmetric multiprocessors. We then use this version to create e cient strategies to 2 greatly di erent different types of difficulties - associated checklist pre x com- tations and generalized sorting. either difficulties are reminiscence extensive, yet in die hire methods. while generalized sorting algorithms in most cases require a wide numberofmemoryaccesses, they areusuallytocontiguousmemorylocations. against this, prex computation algorithms in general require a extra modest qu- tity of reminiscence accesses, yet they're tend to be to non-contiguous reminiscence locations.
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Additional info for Algorithm Engineering and Experimentation: International Workshop ALENEX’99 Baltimore, MD, USA, January 15–16, 1999 Selected Papers
20 15 10 5 2000 4000 6000 8000 Fig. 11. Our implementation: The raw data of Experiment 6 (CPU times in seconds), the fitted curve from the linear regression, and the 95% confidence intervals for the predicted values. 34 M. M¨ uller–Hannemann, A. Schwartz Experiment 7: Mesh refinement. We tested all implementation variants used for the previous experiments also for our real-world instances from the mesh refinement application. In the following table, the second column displays the number of nodes n, followed by the nesting level N and the number of blossoms B observed in our reference implementation (REF) in columns three and four.
In this model, the time required for execution is modeled by five variables, which together describe the amount of time required for computation, the maximum number of memory requests made by a processor, and the maximum number of requests handled by a bank. The difficulty with this model is that the contention it describes depends on specific implementation details such as the memory map, which may be entirely beyond the control of the algorithm designer. A more general version of this model was suggested by Gibbons et al.
The exponent of the estimated asymptotic running time for the d-heap variant appears to be slightly larger than for the simple list implementation, only the constant factors are much in favour for the d-heap. Hence, this is a typical example that extrapolation beyond the range M. M¨ uller–Hannemann, A. Schwartz Running time in seconds log scale Exp. 3: Candidate Search density 16 all CS1 3 14 dual update + traverse traverse all CS2 + update + mark safe CS3 2 12 dual degenerated dual update CS4 10 3 8 3 + + 3+ 6 2 + 43 2 2 2 2 0 10 2 211 212 213 Number of nodes log scale d = 10 3 + 3 + 2 2 2 14 Exp.